This invention relates generally to floating gate memory devices such as an array of flash electrically erasable and programmable read-only memory devices (EEPROMs). More particularly, the present invention relates to a new and improved method for tightening the distribution of control gate threshold voltages of erased cells in 5 Volt-Only flash EEPROMs.
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROMs provide electrical erasing in a small cell size. FIG. 1 illustrates a prior art cross-sectional view of a flash EEPROM cell 10. The EEPROM cell is formed of a substrate 12, typically of a p-type conductivity having embedded therein an n.sup.+ drain region 14 and an n-type double-diffused source region 16. The double-diffused source region 16 is formed of a deeply diffused but lightly doped n-junction 18 and a more heavily doped but shallower n.sup.+ junction 20 embedded within the deep n-junction 18. The deeply diffused n-junction 18 is typically formed by using a phosphorus implant, and the shallower n.sup.+ junction 20 is typically formed by using an arsenic implant after the phosphorus implant.
A relatively thin gate dielectric layer 22 (i.e., oxide having a uniform thickness of about 100 .ANG.) is interposed between the top surface of the substrate 12 and a conductive polysilicon floating gate 24. A polysilicon control gate 26 is insulatively supported above the floating gate 24 by an interpoly dielectric 28. A channel region 30 in the substrate 12 separates the drain region 14 and the source region 16. Further, there are provided terminal pins 15, 17, and 19 for applying a source voltage V.sub.S to the source region 16, a gate voltage V.sub.G to the control gate 26, and a drain voltage V.sub.D to the drain region 14 respectively.
According to conventional operation, a flash EEPROM cell of FIG. 1 is "programmed" by applying a relatively high voltage V.sub.G (approximately +9 volts) to the control gate 26 via the terminal pin 17 and a moderately high voltage V.sub.D (approximately +5 volts) to the drain region 16 via the terminal pin 19 in order to produce "hot" (high energy) electrons into the channel 30 near the drain region 14. The source region 16 is connected to a ground potential (V.sub.S =0) via the terminal pin 15. The hot electrons are generated and accelerated across the gate oxide layer 22 into the floating gate 24, thereby making a threshold voltage of the transistor cell 10 high. This hot electron injection results in an increase of the floating gate threshold by approximately three to five volts. On the other hand, the flash EEPROM cell of FIG. 1 is "erased" by applying a positive voltage V.sub.S to the source region 16 via the terminal 15 while the control gate 26 via the terminal pin 17 is either grounded (V.sub.G =0) or biased to a negative voltage dependent upon the value of the positive voltage V.sub.S. In a "5Volt-Only flash EEPROM" device, the conventional erase bias condition of V.sub.S =+5 V and V.sub.G =-10.68 V is used. The trapped electrons are extracted from the floating gate 24 through the gate oxide layer 22 to the source region 16 by way of Fowler-Nordheim (F-N) tunneling, thereby making the threshold voltage of the transistor cell 10 low.
It is also generally known in the art that the threshold voltage of the single-transistor flash EEPROM cell after erase is variable. A large variation or wide distribution of the threshold voltage V.sub.T after erasure is one of the most considered problems in performances possessed by the EEPROM devices. The distribution of the threshold voltages V.sub.T among the individual cells in the EEPROM array having floating-gate memory cells arranged in rows and columns is caused by processing variations, including localized variations in the tunnel oxide thickness, the areas of tunneling region, and the capacitive coupling ratios between the control gates and the floating gates as well as variations in the strengths of the erasing pulses.
If there exists cells with erased threshold voltages V.sub.T on a given column (bit line) less than zero, or if the floating gates are be positively charged, these cells will be conductive even though their control gates are being grounded. As a result, there will be caused column leakage so as to prevent the proper reading of any other cell in the column of the array containing this cell as well as making programming of the other cells on the same column increasingly more difficult. Under this condition, there is brought about a disadvantage that the data programming characteristic of the memory cell is deteriorated so as to cause endurance failures. Consequently, the number of times that the memory cell may be re-programmed is significantly reduced.
Therefore, the problem of wide distribution of the threshold voltages after erasure for such conventional EEPROM devices is of a major concern since it causes column leakage rendering the cells more difficult to program, thereby significantly limiting the endurance of the cells. As used herein, the term "endurance" refers to the number of times the memory cells in the array may be re-programmed and erased. Consequently, large variations of the threshold voltages after erasure due to over-erasure can greatly reduce the endurance of the memory cells to be less than 100,000.
The inventor has now discovered a new and improved method for tightening the distribution of control gate threshold voltages of erased cells in the 5 Volt-Only flash EEPROMs. This is accomplished by lowering the magnitude of the constant bias voltage applied to the control gate during erasure and reducing simultaneously the value of the load resistor coupled between the positive source voltage V.sub.S and the source region.